1. Field of the Invention
The present invention relates to the field of semiconductor memories and, in particular but not exclusively, to non-volatile semiconductor memories such as, for example, ROMs, EPROMs, EEPROMs and Flash memories.
More specifically, the subject of the invention is a control and timing structure for a semiconductor memory, that is, a structure which is integrated in the memory and which can control the progress of operations inside the memory and can dictate their timing. Even more specifically, the subject of the invention is a control and timing structure for a memory with a functional capability for sequential or xe2x80x9cburstxe2x80x9d reading, particularly performed by sequential and interleaved accesses to memory locations belonging to distinct memory banks.
2. Description of the Related Art
The typical structure of the simplest non-volatile semiconductor memories such as ROMs and EPROMs comprises basically a matrix of memory cells (the memory matrix) in which the cells are arranged in rows (xe2x80x9cword linesxe2x80x9d) and columns (xe2x80x9cbit linesxe2x80x9d), circuits for decoding an address supplied to the memory from the exterior, circuits for selecting the memory cells within the matrix in dependence on the address supplied from the exterior, circuits for reading the contents of the memory cells selected, and output circuits for driving external data lines.
In a conventional non-volatile memory, the sole type of reading access to the memory is random access. The address of the memory location the content of which is to be read is supplied to the memory from the exterior. The decoding circuits and the selection circuits, respectively, decode the address supplied from the exterior and select the memory cells which correspond to that address, that is, they select the rows and the columns. The reading circuits read the contents of the memory cells selected and supply the result of the reading to the output circuits; the datum read in the memory location addressed is placed on the data lines outside the memory.
During random access to the memory, the time required to perform the reading (the memory-access time) is the sum of individual times representative of the durations of the various individual steps which make up the access and datum-extraction process. Basically, these individual steps are: the propagation of the signals along the row and column selection paths, precharging operations, for example, of the columns selected, the step of reading and evaluating the data stored in the memory cells selected, the propagation and transfer of the data read to the output (xe2x80x9cbufferxe2x80x9d) circuits, and the switching thereof.
Each random-access operation involves the execution of all of the above-mentioned individual steps. Precisely for this reason, the access time is quite long or, in any case, is difficult to reduce, even with the use of advanced manufacturing technologies. In particular, the memory-access time for a random reading is longer than the time which is strictly necessary to perform the reading of the content of a memory location.
However, whilst having an access time which is not optimal, the conventional architecture has the advantage that it is straightforward in terms of internal circuit structures and simple from the point of view of the timing (the memory behaves asynchronously), that it can be used relatively easily for the implementation of redundancy structures for xe2x80x9cfunctionally repairingxe2x80x9d memory elements which are not operating, and that it has low consumption.
Italian patent application M12000A002165 entitled xe2x80x9cA semiconductor memory architecturexe2x80x9d, filed by the Applicant on Oct. 6, 2000 describes an architecture for a semiconductor memory which can implement an interleaved sequential reading method on a pair of memory banks in a memory. The contents of this patent application are incorporated herein in its entirety.
The memory architecture which is the subject of the above-mentioned Italian patent application provides for two memory banks containing even memory address locations and odd memory address locations, respectively. Each memory bank has its own circuits for selecting the locations and its own circuits for reading the contents of the locations. An address structure is also provided within the memory and enables the memory to perform a reading of successive locations in sequence by accessing one and the other of the two memory banks alternately, starting from an origin memory location the address of which is supplied to the memory from outside.
In view of the foregoing, the disclosed embodiments of the present invention provide a control and timing structure for a memory, in particular a memory having an architecture of the above-mentioned type.
According to the embodiments of the present invention, this is achieved by means of a timing and control structure for a memory that includes a pair of memory banks each of which is associated with respective circuits for selecting the memory locations of the memory bank and respective circuits for reading the contents of the locations selected, and an internal addressing structure that can execute random-access readings by accessing locations corresponding to addresses supplied to the memory from the exterior, and sequential readings by accessing, in sequence, starting from an origin memory location the address of which is supplied to the memory from outside, memory locations succeeding the origin location and belonging to one and to the other of the memory banks, alternately, and further including:
first circuit means which can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals comprising a first control signal indicative of the presence of an address supplied to the memory from the exterior and a second control signal which, upon switching edges of a first type (xe2x80x9c1xe2x80x9d- greater than xe2x80x9c0xe2x80x9d), supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type (xe2x80x9c0xe2x80x9d- greater than xe2x80x9c1xe2x80x9d), supplies a time base for the execution of the sequential readings,
second circuit means which are controlled by the first circuit means and which, for a random-access reading, generate a first synchronism signal in response to a transition of the first type (xe2x80x9c1xe2x80x9d- greater than xe2x80x9c0xe2x80x9d) in the second control signal,
third circuit means which are sensitive to transitions of the second type (xe2x80x9c0xe2x80x9d- greater than xe2x80x9c1) in the second control signal and which can generate a second synchronism signal upon transitions of the second type, and
fourth circuit means which are controlled by the first circuit means and which supply a stimulus signal to a timing circuit of the memory, the stimulus signal corresponding to the first synchronism signal for a random-access reading, or to the second synchronism signal for a sequential reading.